Using Statistical Assertions to Guide Self-Adaptive Systems

Self-adaptive systems need to monitor themselves, to check their internal behaviour and design assumptions about runtime inputs and conditions. This kind of monitoring for self-adaptive systems can include collecting statistics about such systems themselves which can be computationally intensive (for detailed statistics) and hence time consuming, with possible negative impact on self-adaptive response time. To mitigate this limitation, we extend the technique of in-circuit runtime assertions to cover statistical assertions in hardware. The presented designs implement several statistical operators that can be exploited by self-adaptive systems; a novel optimization is developed for reducing the number of pairwise operators from ON to Olog⁡N. To illustrate the practicability and industrial relevance of our proposed approach, we evaluate our designs, chosen from a class of possible application scenarios, for their resource usage and the tradeoffs between hardware and software implementations

Smart technologies for effective reconfiguration: the FASTER approach

Current and future computing systems increasingly require that their functionality stays flexible after the system is operational, in order to cope with changing user requirements and improvements in system features, i.e. changing protocols and data-coding standards, evolving demands for support of different user applications, and newly emerging applications in communication, computing and consumer electronics. Therefore, extending the functionality and the lifetime of products requires the addition of new functionality to track and satisfy the customers needs and market and technology trends. Many contemporary products along with the software part incorporate hardware accelerators for reasons of performance and power efficiency. While adaptivity of software is straightforward, adaptation of the hardware to changing requirements constitutes a challenging problem requiring delicate solutions. The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a complete methodology to allow designers to easily implement a system specification on a platform which includes a general purpose processor combined with multiple accelerators running on an FPGA, taking as input a high-level description and fully exploiting, both at design time and at run time, the capabilities of partial dynamic reconfiguration. The goal is that for selected application domains, the FASTER toolchain will be able to reduce the design and verification time of complex reconfigurable systems providing additional novel verification features that are not available in existing tool flows

Definition of Estrogen Receptor Pathway Critical for Estrogen Positive Feedback to Gonadotropin-Releasing Hormone Neurons and Fertility

SummaryThe mechanisms through which estrogen regulates gonadotropin-releasing hormone (GnRH) neurons to control mammalian ovulation are unknown. We found that estrogen positive feedback to generate the preovulatory gonadotropin surge was normal in estrogen receptor β knockout (ERβ) mutant mice, but absent in ERα mutant mice. An ERα-selective compound was sufficient to generate positive feedback in wild-type mice. As GnRH neurons do not express ERα, estrogen positive feedback upon GnRH neurons must be indirect in nature. To establish the cell type responsible, we generated a neuron-specific ERα mutant mouse line. These mice failed to exhibit estrogen positive feedback, demonstrating that neurons expressing ERα are critical. We then used a GnRH neuron-specific Pseudorabies virus (PRV) tracing approach to show that the ERα-expressing neurons innervating GnRH neurons are located within rostral periventricular regions of the hypothalamus. These studies demonstrate that ovulation is driven by estrogen actions upon ERα-expressing neuronal afferents to GnRH neurons

Landscapes of Internment: British Prisoner of War Camps and the Memory of the First World War

This article has been accepted for publication and will appear in a revised form, subsequent to peer review and/or editorial input by Cambridge University Press, in Journal of British Studies published by Cambridge University Press. Copyright Cambridge University Press.During the First World War, all the belligerent powers interned both civilian and military prisoners. In Britain alone, over 100,000 people were held behind barbed wire. Despite the scale of this enterprise, interment barely features in Britain's First World War memory culture. By exploring the place of prisoner of war camps within the "militarized environment" of the home front, this article demonstrates the centrality of internment to local wartime experiences. Being forced to share the same environment meant that both British civilians and German prisoners clashed over access to resources, roads and the surrounding landscape. As the article contends, it was only when the British started to employ the prisoners on environmental improvement measures, such as land drainage or river clearance projects, that relations gradually improved. With the end of the war and closure of the camps, however, these deep entanglements were quickly forgotten. Instead of commemorating the complexities of the conflict, Britain's memory culture focused on more comfortable narratives; British military "sacrifice" on the Western Front quickly replaced any discussion of the internment of the "enemy" at home

Combining Imperative and Declarative Hardware Descriptions

This paper describes an approach for hardware development that involves both imperative and declarative descriptions. The imperative descriptions are mainly used for algorithm and application development; they are based on Cobble, a sequential imperative language extended with facilities for parallel computation and arbitrary-sized variables, similar to the Handel-C language. Operators in Cobble can be produced using the declarative language Pebble, which supports efficient bit-level design. We introduce the use of meta-information, such as information about latency and throughput, for Pebble descriptions, to enable Cobble programs to adapt to different implementations of operators in Pebble. The optimisation of designs by transforming the Cobble and Pebble descriptions is presented

Exploring performance enhancement of event-driven processor networks

Event-driven processor networks have been proposed as an effective way of exploiting recent advances in field-programmable technology. This paper explores an approach to enhancing the performance of event-driven processor networks for specific applications: Attaching to the processor network accelerators with custom-designed logic. We present a design flow of this approach, and apply the flow to a heatplate application.</p